Integrated Sensing and Normally-off Computing for Edge Imaging Systems Image
Over past decades, the amount of data that is required to be processed and analyzed by the computing systems has been increasing dramatically to exascale, which brings grand challenges for state-of-the-art computing systems to simultaneously deliver energy-efficient and high-performance computing solutions. Such challenges mainly come from the well-known power wall (i.e. huge leakage power consumption limits the performance growth when technology scales down) and memory wall (including long memory access latency, limited memory bandwidth, and energy-hungry data transfer). Therefore, there is a great need to leverage innovations from both circuit design and computing architecture to build an energy-efficient and high-performance non-Von-Neumann computing platform. In-memory computing has been proposed as a promising solution to reduce massive power-hungry data traffic between computing and memory units, leading to significant improvement in entire system performance.
Ultra-Low Power In-Memory Computing
My research focuses on:
- Explore various in-memory logic circuit designs based on existing memory technologies, including SRAM, DRAM, Magnetic (Spintronic) Memory, Resistive RAM, with low overhead, efficient operation, low latency, etc.
- Explore dual-mode in-memory computing architecture designs that could simultaneously work as memory and in-memory computing units to greatly reduce data communication, fully leverage the highly parallel computing ability of processing-in-memory architecture, and thus improve system performance.
- Explore suitable in-memory computing applications that could be either fully implemented or pre-processed in the proposed in-memory computing platform, including deep neural network, data encryption, image processing, graph processing, bioinformatics, etc.
Supported by NSF.